1. Field of the Invention
The disclosures herein generally relate to semiconductor memory devices, and particularly relates to a semiconductor memory device in which word lines are organized into a hierarchical structure including main word lines and sub-word lines.
2. Description of the Related Art
In a DRAM (dynamic random access memory) that stores data as electric charge accumulated in memory cells comprised of capacitors, there is a need to supply a boost voltage VPP higher than a HIGH level to word lines in order to reliably store the HIGH level in the memory cells at high speed. Further, a negative voltage VNN lower than a ground potential VSS is generally applied to non-selected word lines for the purpose of avoiding leak currents in transistors.
In DRAMs having word lines organized in a hierarchical structure including main word lines and sub-word lines, a selected sub-word line is set to VPP, and unselected sub-word lines are set to VNN. A selected main word line is set to VNN, and unselected main word lines are set to VPP.
FIG. 1 is a drawing showing an example of the circuit configuration of a main word decoder and sub-word decoder. A main word decoder 10 includes PMOS transistors 11 through 13, an NMOS transistor 14, and an inverter 15. A single circuit portion comprised of the PMOS transistors 11 and 12 and the inverter 15 is provided in the main word decoder 10. A plurality (n: integer greater than one) of circuit portions each comprised of the PMOS transistor 13 and the NMOS transistor 14 are provided in the main word decoder 10, so that the main word decoder 10 can drive n main word lines MWL. A memory cell array and peripheral circuit are generally divided into a plurality of memory blocks demarcated according to row addresses. One main word decoder 10 is provided for one memory block.
A signal applied to the gates of the PMOS transistor 13 and NMOS transistor 14 in the main word decoder 10 is a decode signal for selecting a main word line MWL. This decode signal is generated by decoding a row address. At the time of memory access, a decode signal corresponding to a main word line MWL to be selectively activated is set to HIGH.
A sub-word decoder 20 includes a PMOS transistor 21, NMOS transistors 22 and 23, and an inverter 24. For the sake of clarity of illustration, only one sub-word decoder 20 connected to a main word line MWL is shown in FIG. 1. In an actual circuit configuration, however, a plurality (m: integer greater than one) of sub-word decoders 20 corresponding to m row addresses are connected to a single main word line MWL. Further, m sub-word decoders 20 constitute a single set, and a plurality of such sets are connected to a main word line MWL at respective positions in the direction of its extension.
In order to access a selected row address, the main word decoder 10 corresponding to a selected memory block belonging to the selected row address selects a main word line MWL corresponding to the selected row address, and sets the selected main word line MWL to VNN. Further, a sub-word decoder 20 corresponding to the selected row address is selected from the m sub-word decoders 20 connected to a corresponding main word line MWL, followed by setting a signal SO to VPP in this selected sub-word decoder 20. With these settings, the PMOS transistor 21 of the selected sub-word decoder 20 connected to the selected main word line MWL is made conductive to set the potential of a sub-word line SWL to VPP.
In the above-noted main word decoder 10 corresponding to the selected memory block, all the unselected main word lines MWL are set to VPP. With such setting, the PMOS transistor 21 is made nonconductive in the selected sub-word decoders 20 connected to an unselected main word line MWL where the signal SO is set to VPP. In these selected sub-word decoders 20, the NMOS transistor 22 becomes conductive to set the sub-word line SWL to VNN.
In unselected sub-word decoders 20, the signal SO is set to VSS. The output of the inverter 24 is thus set to HIGH to make the NMOS transistor 23 conductive to set the potential of the sub-word line SWL to VNN. In this case, the potential of the sub-word line SWL is VNN regardless of the potential of the main word line MWL (which is either VPP or VNN).
The above description concerns the operation of an activated memory block. In an inactive memory block (i.e., placed in a standby state), all the main word lines MWL are set to VII. The HIGH/LOW state of a signal GIDLCTL controls whether the potential of an inactive (unselected) main word line MWL is set to VII or VPP. The HIGH state of the signal GIDLCTL causes the PMOS transistor 11 to become conductive to select VII whereas the LOW state of the signal GIDLCTL causes the PMOS transistor 12 to become conductive to select VPP. Here, VII is a potential lower than the boost potential VPP, and is generally lower than the power supply voltage VDD applied to the semiconductor memory device.
In the following, for the sake of argument, it is assumed that all the main word lines MWL in an inactive (unselected) memory block are set to VPP. In such a case, the boost potential VPP continues to be applied to the gate of the PMOS transistor 21 in the sub-word decoders 20. When a difference in potential between the drain potential VNN and gate potential VPP of the PMOS transistor 21 is large, a leak current between the source/drain and the well increases, resulting in an increase in current consumption in this inactive (i.e., standby-state) memory block. In order to suppress this leak current, the gate potential of the PMOS transistor 21 is lowered from VPP to VII in inactive memory blocks.
Setting the main word lines MWL to VII in an inactive memory block necessitates an operation by which the potential of the main word lines MWL is increased from VII to VPP upon selecting and activating a memory block at the time of access. This operation serves as a factor to cause current consumption. There may be a case in which a memory block is selectively activated, and is then deactivated immediately after access operation to lower the potential of the main word lines MWL to VII. Another access may occur with respect to this memory block immediately thereafter, thereby consuming an electric current to increase the potential from VII to VPP. It is thus not desirable to create frequent current consumptions by dropping the potential from VPP to VII after each access operation in a memory block that is frequently accessed.
FIG. 2 is a drawing for explaining changes in the potential of a main word line MWL. In an initial state, the memory block of interest is inactive, so that the main word lines MWL are set to VII. Upon start of an operation to access a row address belonging to this memory block of interest, the signal GIDLCTL shown in FIG. 1 is set to HIGH, so that all the main word lines MWL of this memory block are set to VPP. After this, a main word line MWL corresponding to the row address to be accessed is selected and set to VNN. FIG. 2 shows the potential level of this selected main word line MWL.
After the selection of the main word line MWL, the signal SO is changed from VSS to VPP with respect to the sub-word decoders 20 corresponding to the accessed row address. This causes the potential of the sub-word line SWL to change from the unselected potential VNN to the selected active potential VPP. The VPP level of the sub-word line SWL serves to write data to memory cells. The signal So is thereafter changed from VPP to VSS in the sub-word decoders 20, resulting in the potential of the sub-word line SWL being changed from VPP to VNN. The potential of the selected main word line MWL then returns from VNN to VPP. In this state, all the main word lines MWL in the block of interest are set to VPP.
In the example shown in FIG. 2, the potential of all the main word lines MWL are dropped from VPP to VII after the completion of an access operation. This serves to reduce a leak current through the PMOS transistor 21. However, it is undesirable to drop the potential of the main word lines MWL from VPP to VII after each access operation because such drop creates current consumption at every access.
It is conceivable to maintain the potential of the main word lines MWL at VPP for some time period in an accessed memory block after the access operation in order to avoid the occurrence of current consumption at every access due to an increase of potential from VII to VPP. With this arrangement, there is no need to increase the potential of the main word lines MWL from VII to VPP each time this memory block is accessed, thereby reducing excessive current consumption. Keeping the potential of the main word lines MWL at VPP, however, creates another concern that current consumption caused by a leak current through the PMOS transistor 21 cannot be ignored. It is further conceivable to maintain the potential of the main word lines MWL at VPP in memory blocks and then to drop the potential of the main word lines MWL to VII with respect to each memory block for which a refresh operation is completed as refresh operations are successively performed with respect to the memory blocks in a standby state.
FIG. 3 is a drawing for explaining the dropping of the potential of the main word lines MWL with respect to each memory block upon the completion of a refresh operation. FIG. 3 illustrates an example in which 4 memory blocks BLK0 through BLK3 are provided. An active period for memory access appears first, followed by a standby period in which no memory access is performed. Each row in FIG. 3 shows whether the potential of the main word lines MWL are VPP or VII with respect to a corresponding one of the memory blocks BLK0 through BLK3.
In FIG. 3, a first access operation in the active period is a read operation (RD-BLK0) with respect to the memory block BLK0. As a result of this access operation, the potential of the main word lines MWL are set to VPP in the memory block BLK0, and are maintained at VPP even after this access operation. A second access operation in the active period is a read operation (RD-BLK2) with respect to the memory block BLK2. As a result of this access operation, the potential of the main word lines MWL are set to VPP in the memory block BLK2, and are maintained at VPP even after this access operation.
In the standby period, the memory blocks BLK0 through BLK3 are successively refreshed. This may be a refresh operation automatically performed within the DRAM. In a period designated as REFxWL-BLK0, all the sub-word lines SWL are successively selected and refreshed in the memory block BLK0. After the completion of these refresh operations for this memory block, the potential of all the main word lines MWL of the memory block BLK0 is dropped from VPP to VII. In a period designated as REFxWL-BLK1, thereafter, all the sub-word lines SWL are successively selected and refreshed in the memory block BLK1. The memory block BLK1 is activated for these refresh operations, and all the main word lines MWL are set to VPP. After the completion of these refresh operations for this memory block, the potential of all the main word lines MWL of the memory block BLK1 is dropped from VPP to VII.
In a period designated as REFxWL-BLK2, all the sub-word lines SWL are successively selected and refreshed in the memory block BLK2. After the completion of these refresh operations for this memory block, the potential of all the main word lines MWL of the memory block BLK2 is dropped from VPP to VII. In a period designated as REFxWL-BLK3, further, all the sub-word lines SWL are successively selected and refreshed in the memory block BLK3. The memory block BLK3 is activated for these refresh operations, and all the main word lines MWL are set to VPP. After the completion of these refresh operations for this memory block, the potential of all the main word lines MWL of the memory block BLK3 is dropped from VPP to VII.
Through the operations shown in FIG. 3 as described above, it is possible to eliminate the excessive current consumption operation that increases the potential of the main word lines MWL from VII to VPP each time a memory block is accessed. At the same time, the current consumption caused by leak currents in inactive memory blocks can be reduced to some exent. The above-described operations, however, may not be effective in terms of its advantageous effect of reducing leak currents in inactive memory blocks when the memory blocks are accessed in a particular manner.
FIG. 4 is a drawing for explaining a case in which the effect of reducing leak currents is not sufficient when dropping the potential of the main word lines MWL with respect to each memory block upon the completion of a refresh operation. In the example shown in FIG. 4, access operations are successively performed with respect to the memory blocks BLK0 through BLK3, resulting in the main word lines MWL being maintained at VPP in all the memory blocks BLK0 through BLK3.
In the standby period in which no memory access is performed, the memory blocks BLK0 through BLK3 are successively refreshed. This may be a refresh operation automatically performed within the DRAM as previously described. In the same manner as in FIG. 3, after the completion of refresh operations for a given memory block, the potential of all the main word lines MWL of this memory block is dropped from VPP to VII.
When operations are performed in the manner as shown in FIG. 4, the period in which the main word lines MWL are set to VPP in all the memory blocks continues for some time. During this period, the effect of reducing leak currents in inactive memory blocks is nonexistent. Even after the successive refresh operations for the memory blocks BLK0 through BLK3 are started, the main word lines MWL continue to be at VPP in at least one of the memory blocks until all the sub-word lines SWL of all the memory blocks are refreshed. The period required to refresh all the sub-word lines SWL of all the memory blocks is shown as tREF in FIG. 4. There may be a case in which a standby period continues for a duration substantially equal to tREF, immediately followed by an active period in which random memory accesses occur in such a manner as to access addresses evenly across the memory space, and further followed by a standby period lasting for a duration substantially equal to tREF. In such a case, the effect of leak current reduction will be extremely small.
Accordingly, there is a need for a semiconductor memory device that can eliminate the excessive current consumption operation that increases the potential of main word lines each time a memory block is accessed while sufficiently maintaining the effect of leak current reduction in inactive memory blocks.
[Patent Document 1] Japanese Patent Application Publication No. 2000-149564